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Firmware Engineer – SerDes PHY (all levels)

Qualcomm · Toronto, Ontario, Canada

Posted 2026-09-03 · Verified live 2026-09-19

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About this role

<h2><br><b>Company:</b></h2>Qualcomm Canada ULC<p></p><h2><b>Job Area:</b></h2>Engineering Group, Engineering Group &gt; Software Engineering<p></p><p><u><b>General Summary:</b></u></p><p>As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Software Engineer, you will design, develop, create, modify, and validate embedded and cloud edge software, applications, and/or specialized utility programs that launch cutting-edge, world class products that meet and exceed customer needs. Qualcomm Software Engineers collaborate with systems, hardware, architecture, test engineers, and other teams to design system-level software solutions and obtain information on performance requirements and interfaces. <b>Replacement Position</b></p><p></p><p><u><b>Minimum Qualifications:</b></u></p>• Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Software Engineering or related work experience. <br> OR<br>Master's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Software Engineering or related work experience.<br> OR<br>PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Software Engineering or related work experience.<br><br>• 3+ years of work experience with Programming Language such as C, C++, Java, Python, etc.<p></p><p></p><p>We’re building the world’s most advanced SerDes PHY for use in AI data centers and beyond.&nbsp;The&nbsp;<b>Embedded Software /&nbsp;Firmware Team at&nbsp;Qualcomm</b>&nbsp;develops critical embedded software that powers high-performance multi-standard Serializer/Deserializer&nbsp;(SerDes) PHY IP used in next-generation data center, AI/ML, automotive, and compute applications. Our SerDes IPs support standards such as PCIe, Ethernet, CXL,&nbsp;and&nbsp;are integrated into SoCs,&nbsp;ASICs, and chiplets&nbsp;built by leading semiconductor companies around the world.&nbsp;</p><p>The firmware team owns the full embedded software stack that controls the SerDes hardware, including low-level embedded firmware, customer-facing C SDKs,&nbsp;demo &amp;&nbsp;automation scripts, and interactive tools. As a key enabler of silicon bring-up, validation, and production deployment, we work closely with hardware, systems, DV,&nbsp;validation,&nbsp;and application teams across the product lifecycle—from early development to high-volume manufacturing.&nbsp;</p><p>We are looking for an experienced Firmware Engineer to lead firmware architecture, development, integration, and bring-up for our SerDes PHY portfolio. The ideal candidate has driven firmware definition, architecture, and development starting from the RTL/digital design phase with EDA tool/simulator integration, all the way through to the post-silicon phase with device-level bring-up and debug. This is a highly collaborative role: you will work with hardware, systems, and software teams to drive requirements and successful chip bring-up; with firmware and embedded software engineers to drive code re-use across the organization; and with program managers to identify and meet deadlines. This individual will be instrumental in building next-generation&nbsp;SERDES PHY&nbsp;IP and semiconductors that meet Qualcomm’s high performance and quality standards.&nbsp;</p><p></p><p><b>What You Can Expect</b>&nbsp;</p><p>Core responsibilities for the firmware team include:&nbsp;</p><ul><li><p>Embedded firmware running on RISC-V-based controllers that manage Qualcomm’s advanced SerDes&nbsp;datapaths&nbsp;</p></li></ul><ul><li><p>Python and C SDKs provided to internal SoC teams and external customers for SerDes bring-up, calibration, tuning, and diagnostics&nbsp;</p></li></ul><ul><li><p>Python-based lab tools and GUIs for interactive debug, register access, and validation&nbsp;</p></li></ul><ul><li><p>Build, regression, and CI infrastructure to ensure code quality and full coverage.</p></li><li><p></p></li></ul><p>You’ll play a key leadership role in delivering robust, production-quality firmware for SerDes PHY IP. You’ll help define architecture, drive features end-to-end, coordinate across cross-functional teams, and directly influence the design and usability of&nbsp;Qualcomm’s&nbsp;designs.&nbsp;</p><p>&nbsp;</p><p><b>In this position, you will be:&nbsp;</b></p><ul><li><p>Technical or project lead for SerDes firmware on a major IP program, working with a team (2–8 engineers) through planning, development, validation, and customer delivery&nbsp;</p></li></ul><ul><li><p>Owning the entire firmware lifecycle for SerDes PHY, from pre-silicon design through post-silicon validation and optimization&nbsp;</p></li></ul><ul><li><p>Gathering requirements, studying high-level designs, developing device interface functions, and turning small building blocks into higher-level firmware system design&nbsp;</p></li></ul><ul><li><p>Architecting and implementing embedded C/C++ firmware for hardware calibration, training algorithms, DSP adaptations, and link state management&nbsp;</p></li></ul><ul><li><p>Working with multi-functional teams — ASIC/digital design, digital verification, software, and systems engineering — to define detailed bring-up and validation requirements and meet performance goals&nbsp;</p></li></ul><ul><li><p>Communicating requirements and coordinating execution across multiple teams and sites&nbsp;</p></li></ul><ul><li><p>Translating bring-up and validation requirements into efficient C/C++ firmware code and well-structured software organization&nbsp;</p></li></ul><ul><li><p>Translating protocol specifications (e.g. PCIe, Ethernet, CXL, UCIe) or custom system-level requirements into internal firmware architecture and documentation&nbsp;</p></li></ul><ul><li><p>Developing test and debug capabilities that help guide hardware design decisions for future product iterations&nbsp;</p></li></ul><ul><li><p>Debugging complex lab and field issues in conjunction with hardware, applications, and validation teams, and driving low-level SW, silicon, and HW issues to root cause and closure&nbsp;</p></li></ul><ul><li><p>Driving multi-functional teams and partners to address integration and bring-up challenges, ensuring chips are seamlessly brought up, validated, tested, and meet product and business requirements&nbsp;</p></li></ul><ul><li><p>Planning and developing test cases that improve reliability and release quality for internal and external stakeholders, and ensuring they run continuously in regression&nbsp;</p></li></ul><ul><li><p>Working with external vendors and customers to ensure requirements are met and releases are of high quality&nbsp;</p></li></ul><ul><li><p>Driving and collaborating across functions to define FW milestones, plan sprints, close tickets, and deliver reliable, high-quality features&nbsp;</p></li></ul><ul><li><p>Implementing industry best practices and documenting firmware and hardware design specifications and decisions&nbsp;</p></li></ul><ul><li><p>Mentoring junior engineers, promoting team building, and driving continuous improvement in processes and techniques&nbsp;</p></li></ul><ul><li><p>Demonstrating full ownership of assigned systems/components, managing timelines and resolving project challenges to meet program timing&nbsp;</p></li></ul><ul><li><p>Staying current with advancements in the semiconductor industry and incorporating relevant innovations into our processes&nbsp;</p></li></ul><ul><li><p>Supporting development and silicon bring-up across Qualcomm teams and other sites&nbsp;</p></li></ul><p>&nbsp;</p><p><b>Example&nbsp;Problems You’ll Solve</b>&nbsp;</p><ul><li><p>Mentoring a junior engineer through a hard-to-reproduce PHY calibration bug seen in customer silicon&nbsp;</p></li></ul><ul><li><p>Developing architecture and state machines to handle multi-lane synchronization or adaptive equalization across dynamic conditions&nbsp;</p></li></ul><ul><li><p>Porting a high-level MATLAB or Python SerDes calibration algorithm to optimized fixed-point firmware&nbsp;</p></li></ul><ul><li><p>Creating a SerDes diagnostics framework accessible via both SDK and GUI&nbsp;</p></li></ul><ul><li><p>Using simulation environments, EDA tool integration, and FPGA emulation to validate FW behavior before&nbsp;tapeout&nbsp;</p></li></ul><ul><li><p>Building error monitoring and board/interface configuration APIs that make link health observable to SoC software teams&nbsp;</p></li></ul><ul><li><p>Standing up a regression suite that catches link-training regressions before a customer release ships&nbsp;</p></li></ul><ul><li><p>Working with IP hardware architects to influence future revisions based on field debug learnings&nbsp;</p></li></ul><p>&nbsp;</p><p><b>What We’re Looking For</b></p><ul><li><p>BS/MS in Computer Science, Electrical Engineering, Computer Engineering, or a related field&nbsp;</p></li></ul><ul><li><p>7+ years of experience in embedded C/C++ firmware development for hardware IP or SoCs, with strong proficiency in C/C++ and Python&nbsp;</p></li></ul><ul><li><p>Hands-on experience with embedded architectures such as ARM, RISC-V, or MIPS, and with low-level programming on bare metal, RTOS, BIOS/UEFI firmware, Linux kernel, or device drivers&nbsp;</p></li></ul><ul><li><p>Technical or team leadership experience in embedded software projects from spec to production&nbsp;</p></li></ul><ul><li><p>Deep understanding of microcontroller architecture (RISC-V a plus), memory-mapped registers, ISRs, and boot flows&nbsp;</p></li></ul><ul><li><p>Systems mindset and experience developing SW/FW to control analog, digital, and mixed-signal circuits&nbsp;</p></li></ul><ul><li><p>Experience with SerDes, Ethernet, PCIe, CXL, or D2D/UCIe/chiplet products and communication systems&nbsp;</p></li></ul><ul><li><p>Strong lab debug skills, working directly on silicon with scopes, JTAG debuggers, I2C/SPI tools, analyzers, and custom tooling, including bring-up and diagnostics of high-speed signals&nbsp;</p></li></ul><ul><li><p>Familiarity with industry-standard EDA tools and methodologies used for digital verification, and with HDLs such as Verilog and&nbsp;SystemVerilog&nbsp;</p></li></ul><ul><li><p>Familiarity with git and modern software development methodologies&nbsp;</p></li></ul><ul><li><p>Excellent organizational and communication skills, a willingness to learn, and the ability to collaborate across functions and geographies&nbsp;</p></li></ul><p>&nbsp;</p><p><b>Preferred Experience:</b>&nbsp;</p><ul><li><p>Knowledge of SerDes and high-speed IO standards (PCIe, Ethernet, UCIe, CXL, etc.)&nbsp;</p></li></ul><ul><li><p>Experience with calibration algorithms, signal conditioning, and adaptive feedback control in hardware&nbsp;</p></li></ul><ul><li><p>Experience in silicon bring-up and post-silicon debug&nbsp;</p></li></ul><ul><li><p>Experience in pre-silicon firmware development (DV, emulation, etc.)&nbsp;</p></li></ul><ul><li><p>Knowledge of RTOS or bare-metal FW architectures, including embedded Linux development,&nbsp;Buildroot/Yocto, and&nbsp;RTOSes&nbsp;such as Zephyr and&nbsp;FreeRTOS&nbsp;</p></li></ul><ul><li><p>Knowledge of peripherals and protocols such as 1G/10G Ethernet, DDR, I2C, SPI/QSPI, MIPI/CSI, GMSL, A2B</p></li></ul>

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