Senior Engineer, FPGA

<p><strong>Company Overview</strong></p>

<p><strong>Ambiq</strong>&nbsp;is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.</p>

<p>Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.</p>

<p>Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.</p>

<p>We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.</p>

<p>At Ambiq, we live by five values:&nbsp;<strong>Innovate. Collaborate. Focus. Learn. Achieve.</strong></p>

<p>If that's you, join us — the intelligence everywhere revolution starts here.</p>

<p>&nbsp;</p><p>As the Senior Engineer, FPGA<strong>&nbsp;</strong>at&nbsp;Ambiq, you will drive the&nbsp;development and&nbsp;rendering&nbsp;of FPGA images in support of our pre-silicon prototyping&nbsp;environments.&nbsp;&nbsp;</p>

<p>&nbsp;</p>

<p>In&nbsp;this role, you&nbsp;will work&nbsp;with our&nbsp;SoC design,&nbsp;software&nbsp;development,&nbsp;design&nbsp;verification, and system test teams as our primary internal customers&nbsp;for the FPGA images.&nbsp;&nbsp;</p>

<p>&nbsp;</p>

<p>The successful candidate&nbsp;will have&nbsp;experience in RTL design, verification, and FPGA/Prototyping platform creation to support Design Verification, Validation, Software Development and System Test at the pre-silicon phase.&nbsp;&nbsp;</p>

<p>The person in this role&nbsp;must be&nbsp;comfortable working with RTL to implement specialized changes to the SoC database for the FPGA development flow. This&nbsp;role will require defining and implementing internal and external&nbsp;FPGA&nbsp;timing constraints to enable repeated delivery of design iterations to the software and validation teams.&nbsp;The candidate&nbsp;will&nbsp;be required&nbsp;to&nbsp;debug RTL&nbsp;designs&nbsp;using FPGA tools, external logic analyzers, and protocol analyzers.&nbsp;</p>

<p><strong>Responsibilities</strong>&nbsp;</p>

<ul>

<li>Implement&nbsp;and&nbsp;debug&nbsp;FPGA&nbsp;designs&nbsp;on&nbsp;AMD FPGA&nbsp;based&nbsp;prototyping&nbsp;platforms&nbsp;using&nbsp;Xilinx&nbsp;Vivado&nbsp;and&nbsp;ISE&nbsp;tools.&nbsp;</li>

</ul>

<ul>

<li>Implement&nbsp;and&nbsp;debug&nbsp;FPGA&nbsp;designs&nbsp;on&nbsp;a Stratix-10&nbsp;development&nbsp;board&nbsp;using&nbsp;Intel&nbsp;Quartus&nbsp;prime&nbsp;Pro.&nbsp;&nbsp;</li>

</ul>

<ul>

<li>Support a regression test-suite consisting of system-level test cases to&nbsp;validate&nbsp;updated FPGA builds.&nbsp;&nbsp;</li>

</ul>

<ul>

<li>Assist&nbsp;development&nbsp;teams&nbsp;in&nbsp;reproduction,&nbsp;triage,&nbsp;and&nbsp;debug&nbsp;of&nbsp;issues&nbsp;both&nbsp;pre-silicon&nbsp;and&nbsp;post-silicon&nbsp;</li>

</ul>

<ul>

<li>Define and implement timing constraints.&nbsp;</li>

</ul>

<p><strong>Qualifications</strong>&nbsp;</p>

<ul>

<li>BSEE or BSCE with&nbsp;6+ years of SoC design, verification, or related work experience and 8+ years of experience&nbsp;of&nbsp;FPGA design, bring-up, debugging, and verification.&nbsp;</li>

</ul>

<ul>

<li>In-depth knowledge of top-down FPGA development process with recent experience with FPGA-based prototyping on an FPGA development platform.&nbsp;</li>

</ul>

<ul>

<li>Solid experience with&nbsp;defining&nbsp;timing constraints&nbsp;for Static Timing Analysis.&nbsp;</li>

</ul>

<ul>

<li>Some familiarity with Cadence SoC design flow.&nbsp;</li>

</ul>

<ul>

</ul>