Principal Emulation Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Principal Emulation Engineer — San Jose, CA 

Role Overview 

As a Principal Emulation Engineer, you will build and operate emulation environments that let verification teams stress-test complex ASICs before silicon. You’ll partner closely with design, verification, firmware, and systems engineers to model hardware-software interactions, exercise high-speed protocols, and isolate issues across RTL, transactors, test environments, and code. Your hands-on leadership will turn difficult debug problems into actionable fixes and improve confidence in each product milestone. 

Astera Labs is accelerating the infrastructure behind AI by delivering purpose-built connectivity solutions for rack-scale systems. In this role, you’ll help validate the switching, PCIe, Ethernet, memory, and storage interfaces that connect the compute fabric—enabling faster bring-up, stronger interoperability, and more reliable platforms as the company scales. 

Key Responsibilities 

• Emulation and Prototyping 

• Architect, build, and maintain emulation environments for complex ASICs and SoCs. 

• Integrate RTL, transactors, protocol models, software, and test infrastructure to enable meaningful hardware-software co-simulation. 

• Enable verification teams to stress-test designs with scalable, repeatable emulation workflows. 

• Develop reusable models, utilities, and debug methodologies that accelerate pre-silicon validation. 

• Protocol and SoC Verification 

• Verify hardware-software interfaces and system behaviors in partnership with logic designers, firmware engineers, and verification teams. 

• Exercise and debug PCI Express Gen 3 and above, Ethernet, DDR, NVMe, SPI, I2C/I3C, and similar interfaces.